The present invention relates generally to computer memory, and more particularly, to adaptive error correction in a memory system.
Computer systems often require a considerable amount of high speed memory to hold information, such as data and programs, when a computer is powered and operational. This information is normally binary, composed of patterns of 1's and 0's known as bits of data. The bits of data are typically stored in separate cells of memory devices. Current and emerging memory and storage technologies may experience single cell bit errors during a storage interval. In dynamic random access memory (DRAM) technology, these types of errors can be caused by cell leakage, alpha particle collision events, variable retention phenomena and several other means. DRAM is a type of volatile memory that uses capacitors to store bits as levels of charge. DRAM requires periodic refreshing to maintain correct charge levels within memory cells. DRAM read operations are typically destructive in that the process of reading cell values can change the charge level per cell. To restore the correct charge level as part of a read operation, a write-back operation is performed such that the intended bit state of each cell is maintained.
Current state of the art systems typically resolve memory bit errors through error correction techniques at the system level. As technology scaling results in denser memory cell counts per memory device, single cell error rates are likely to increase in memory systems.